DDR2 SDRAM or double-data-rate two synchronous dynamic random access memory is a random access memory technology used in electronic engineering for high speed storage of the working data of a computer or other digital electronic device.
It is a part of the SDRAM (synchronous dynamic random access memory) family of technologies, which is one of many DRAM (dynamic random access memory) implementations, and is an evolutionary improvement over its predecessor, DDR SDRAM.
Its primary benefit is the ability to operate the external data bus twice as fast as DDR SDRAM. This is achieved by improved bus signaling, and by operating the memory cells at half the clock rate (one quarter of the data transfer rate), rather than at the clock rate as in the original DDR. DDR2 memory at the same clock speed as DDR will provide the same bandwidth but markedly higher latency, providing worse performance.
Like all SDRAM implementations, DDR2 stores memory in memory cells that are activated with the use of a clock signal to synchronize their operation with an external data bus. Like DDR before it, DDR2 cells transfer data both on the rising and falling edge of the clock (a technique called "double pumping"). The key difference between DDR and DDR2 is that in DDR2 the bus is clocked at twice the speed of the memory cells, so four bits of data can be transferred per memory cell cycle. Thus, without speeding up the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR.
DDR2's bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is 4 bits deep, whereas it is 2 bits deep for DDR and 8 bits deep for DDR3. While DDR SDRAM has typical read latencies of between 2 and 3 bus cycles, DDR2 may have read latencies between 4 and 6 cycles. Thus, DDR2 memory must be operated at twice the bus speed to achieve the same latency.
Another cost of the increased speed is the requirement that the chips are packaged in a more expensive and more difficult to assemble BGA package as compared to the TSSOP package of the previous memory generations such as DDR SDRAM and SDR SDRAM. This packaging change was necessary to maintain signal integrity at higher speeds.
Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8 V compared to DDR's 2.5 V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available speed.
According to JEDEC the maximum recommended voltage is 1.9 volts and should be considered the absolute maximum when memory stability is an issue (such as in servers or other mission critical devices). In addition, JEDEC states that memory modules must withstand up to 2.3 volts before incurring permanent damage (although they may not actually function correctly at that level).
Chips and modules
For use in computers, DDR2 SDRAM is supplied in DIMMs with 240 pins and a single locating notch. DIMMs are identified by their peak transfer capacity (often called bandwidth).
| Standard name | Memory clock | Cycle time | I/O Bus clock | Data transfers per second | Module name | Peak transfer rate |
| DDR2-400 | 100 MHz | 10 ns | 200 MHz | 400 Million | PC2-3200 | 3200 MB/s |
| DDR2-533 | 133 MHz | 7.5 ns | 266 MHz | 533 Million | PC2-4200 PC2-43001 | 4266 MB/s |
| DDR2-667 | 166 MHz | 6 ns | 333 MHz | 667 Million | PC2-5300 PC2-54001 | 5333 MB/s |
| DDR2-800 | 200 MHz | 5 ns | 400 MHz | 800 Million | PC2-6400 | 6400 MB/s |
| DDR2-1066 | 266 MHz | 3.75 ns | 533 MHz | 1066 Million | PC2-8500 PC2-86001 | 8533 MB/s |
Note: DDR2-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC2-xxxx denotes theoretical bandwidth (though it is often rounded up or down), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR2 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.
1 Some manufacturers label their DDR2 sticks as PC2-4300 instead of PC2-4200, and PC2-5400 instead of PC2-5300. At least one manufacturer has reported this reflects successful testing at a faster-than standard speed, whilst others simply use the alternate rounding as the name, as described above.
In addition to bandwidth and capacity variants, modules can
- Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC2-4200 ECC is a PC2-4200 module with ECC.
- Be "registered", which improves signal integrity (and hence potentially clock speed and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. "unbuffered") RAM may be identified by an additional U in the designation. PC2-4200R is a registered PC2-4200 module, PC2-4200R ECC is the same module but with additional ECC.
- Be Fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.
Note: registered and unbuffered SDRAM generally cannot be mixed on the same channel.
